`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: CBICR, Tsinghua Univ.
// Engineer: Hongyi Li
// 
// Create Date: 2024/12/24 09:51:23
// Design Name: 
// Module Name: Router_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module NetworkLine
#(
    parameter DataWidth = 'd32,
    parameter FifoDepth = 'd4,
    parameter VCNumber  = 'd4,
    parameter CoreNum   = 'd4
)(
    input                                       clk, rst_n,
    input   [CoreNum * DataWidth-1:0]           i_data_l,
    output  [CoreNum * DataWidth-1:0]           o_data_l
);

wire [13:0] fwd_lookahead [0:CoreNum]; // W -> E
wire [13:0] bwd_lookahead [0:CoreNum]; // W <- E

wire [VCNumber*$clog2(FifoDepth)  -1:0] fwd_credit [0:CoreNum]; // W -> E
wire [VCNumber*$clog2(FifoDepth)  -1:0] bwd_credit [0:CoreNum]; // W <- E

wire [DataWidth -1:0] fwd_data   [0:CoreNum]; // W -> E
wire [DataWidth -1:0] bwd_data   [0:CoreNum]; // W <- E

wire [DataWidth -1:0] i_loc_data [0:CoreNum-1];
wire [DataWidth -1:0] o_loc_data [0:CoreNum-1];

/*
    fwd_data[i] --> +---+ --> fwd_data[i+1] --> +-----+
                 W  | i |  E                    | i+1 |
    bwd_data[i] <-- +---+ <-- bwd_data[i+1] <-- +-----+

    fwd_crdt[i] --> +---+ --> fwd_crdt[i+1] --> +-----+
                 W  | i |  E                    | i+1 |
    bwd_crdt[i] <-- +---+ <-- bwd_crdt[i+1] <-- +-----+
 */

assign fwd_lookahead[0] = 0;
assign fwd_credit[0] = 0;
assign fwd_data[0] = 0;

assign bwd_lookahead[CoreNum] = 0;
assign bwd_credit[CoreNum] = 0;
assign bwd_data[CoreNum] = 0;

genvar i;
generate
    for (i = 0; i < CoreNum; i = i + 1) begin

        assign i_loc_data[i] = i_data_l[(i+1)*DataWidth-1 : i*DataWidth];
        assign o_data_l[(i+1)*DataWidth-1 : i*DataWidth] = o_loc_data[i];

        SmartRouter #(
            .DataWidth('d32),
            .TokenWidth('d1),
            .LkAheadWidth('d14),
            .FifoDepth('d4),
            .VCNumber('d4),
            .CoreID(i)
        ) RtrU (
            .clk(clk), .rst_n(rst_n),
            // I-Token
            .i_tokens({5'b11111}), // EWNSL
            // I-LookAhead
            .i_lookahead_e(bwd_lookahead[i+1]), .i_lookahead_w(fwd_lookahead[i]),
            .i_lookahead_n(0), .i_lookahead_s(0),
            .i_lookahead_l(0),
            // I-Data
            .i_data_e(bwd_data[i+1]), .i_data_w(fwd_data[i]),
            .i_data_n(0), .i_data_s(0),
            .i_data_l(i_loc_data[i]),
            // I-Credit
            .i_credit_e(bwd_credit[i+1]),  .i_credit_w(fwd_credit[i]), 
            .i_credit_n(0), .i_credit_s(0), .i_credit_l(0), 
            // O-LookAhead
            .o_lookahead_e(fwd_lookahead[i+1]), .o_lookahead_w(bwd_lookahead[i]),
            .o_lookahead_n(), .o_lookahead_s(),
            .o_lookahead_l(),
            // O-Data
            .o_data_e(fwd_data[i+1]), .o_data_w(bwd_data[i]), 
            .o_data_n(), .o_data_s(), 
            .o_data_l(o_loc_data[i]),
            // O-Credit
            .o_credit_e(fwd_credit[i+1]), .o_credit_w(bwd_credit[i]), 
            .o_credit_n(), .o_credit_s()
        );
    end
endgenerate

 
endmodule
